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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
Rev. 05 -- 15 December 2009 Product data sheet
1. General description
The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC915/916/917 in order to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
I 2 kB byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory. I Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured to toggle a port output upon timer overflow or to become a PWM output. I 23-bit system timer that can also be used as a Real-Time clock. I 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog comparators with selectable reference. I Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. I SPI communication port (P89LPC916). I Internal RC oscillator option allows operation without external oscillator components. The RC oscillator (factory calibrated to 1 %) option is selectable and fine tunable. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916, P89LPC917).
2.2 Additional features
I 14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages. I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
I Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Watchdog timer with separate on-chip oscillator, requiring no external components. The Watchdog prescaler is selectable from 8 values. I Low voltage brownout detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. I Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). I Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. I Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. I Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. I LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC915/916/917 when internal reset option is selected. I Four interrupt priority levels. I Five (P89LPC916), six (P89LPC915), or seven (P89LPC917) keypad interrupt inputs. I Second data pointer. I Schmitt trigger port inputs. I Emulation support.
3. Product comparison overview
Table 1 highlights the differences between these three devices. For a complete list of device features, please see Section 2 "Features".
Table 1. Product comparison overview Comparator 2 output X X SPI X T1 toggle/PWM CLKOUT X X INT1 X X KBI 6 5 7
Type number P89LPC915 P89LPC916 P89LPC917
P89LPC915_916_917_5
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Product data sheet
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
4. Ordering information
Table 2. Ordering information Package Name P89LPC915FDH P89LPC915FN P89LPC915HDH P89LPC916FDH P89LPC917FDH TSSOP14 DIP14 TSSOP14 TSSOP16 TSSOP16 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic dual in-line package; 14 leads (300 mil) plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT402-1 SOT27-1 SOT402-1 SOT403-1 SOT403-1 Type number
4.1 Ordering options
Table 3. Ordering options[1] Temperature range -40 C to +85 C Frequency 0 MHz to 18 MHz Type number P89LPC915FDH P89LPC915FN P89LPC916FDH P89LPC917FDH P89LPC915HDH
[1]
-40 C to +125 C
Please contact your local NXP sales office for availability of extended temperature (-40 C to +125 C) versions of the P89LPC916 and P89LPC917 devices.
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
5. Block diagram
P89LPC915
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
TXD 2 kB CODE FLASH internal bus UART RXD
SCL 256 BYTE DATA RAM I2C SDA AD10 AD11 AD12 AD13 DAC1
P1[5:0]
PORT 1 CONFIGURABLE I/O
ADC1/DAC1
P0[5:0]
PORT 0 CONFIGURABLE I/O
REAL TIME CLOCK/ SYSTEM TIMER
TIMER 0 TIMER 1 KEYPAD INTERRUPT
T0
WATCHDOG TIMER AND OSCILLATOR
ANALOG COMPARATORS
CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF
PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR
CPU clock
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa822
Fig 1.
P89LPC915 block diagram
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
4 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC916
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
TXD 2 kB CODE FLASH internal bus UART RXD
SCL 256 BYTE DATA RAM I2C SDA AD10 AD11 AD12 AD13 DAC1 SPICLK MOSI MISO SS
P2[5:2]
PORT 2 CONFIGURABLE I/O
ADC1/DAC1
P1.5, P1[3:0]
PORT 1 CONFIGURABLE I/O
SPI
P0[5:1]
PORT 0 CONFIGURABLE I/O
REAL TIME CLOCK/ SYSTEM TIMER
TIMER 0 TIMER 1 KEYPAD INTERRUPT
T0
WATCHDOG TIMER AND OSCILLATOR
ANALOG COMPARATORS
CIN2B CIN2A CIN1A CIN1B CMPREF
PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR
CPU clock
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa823
Fig 2.
P89LPC916 block diagram
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
5 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC917
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
TXD 2 kB CODE FLASH internal bus UART RXD
SCL 256 BYTE DATA RAM I2C SDA AD10 AD11 AD12 AD13 DAC1
P2.2
PORT 2 CONFIGURABLE I/O
ADC1/DAC1
P1[5:0]
PORT 1 CONFIGURABLE I/O
REAL TIME CLOCK/ SYSTEM TIMER
P0.7, P[5:0]
PORT 0 CONFIGURABLE I/O
TIMER 0 TIMER 1
T0 T1
KEYPAD INTERRUPT
ANALOG COMPARATORS
CMP2 CIN2B CIN2A CIN1A CIN1B CMPREF
WATCHDOG TIMER AND OSCILLATOR
PROGRAMMABLE OSCILLATOR DIVIDER external clock input ON-CHIP RC OSCILLATOR clkout
CPU clock
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
002aaa824
Fig 3.
P89LPC917 block diagram
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
6. Functional diagram
VDD VSS
KBI0 AD10 AD11 AD12 DAC1 AD13 CLKIN KBI1 KBI2 KBI3 KBI4 KBI5
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF PORT 0 PORT 1
TXD RXD T0 SCL SDA
P89LPC915
INT0 INT1 RST
002aaa828
Fig 4.
P89LPC915 functional diagram
VDD
VSS
TXD AD10 AD11 AD12 DAC1 AD13 CLKIN KBI1 KBI2 KBI3 KBI4 KBI5 CIN2B CIN2A CIN1B CIN1A CMPREF PORT 0 PORT 1 RXD T0 INT0 SCL SDA
P89LPC916
RST MOSI MIS0 PORT 2 SS SPICLK
002aaa829
Fig 5.
P89LPC916 functional diagram
P89LPC915_916_917_5
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Product data sheet
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
VDD
VSS
KBI0 AD10 AD11 AD12 DAC1 AD13 CLKIN CLKOUT KBI1 KBI2 KBI3 KBI4 KBI5 KBI7
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF T1 PORT 2 PORT 0 PORT 1
TXD RXD T0 SCL SDA
P89LPC917
INT0 INT1 RST
002aaa830
Fig 6.
P89LPC917 functional diagram
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
8 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
7. Pinning information
7.1 Pinning
P0.1/CIN2B/KBI1/AD10 P0.0/CMP2/KBI0 P1.5/RST VSS P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL
1 2 3 4 5 6 7
002aaa825
14 P0.2/CIN2A/KBI2/AD11 13 P0.3/CIN1B/KBI3/AD12 12 P0.4/CIN1A/KBI4/AD13/DAC1
P89LPC915
11 P0.5/CMPREF/KBI5/CLKIN 10 VDD 9 8 P1.0/TXD P1.1/RXD
Fig 7.
P89LPC915 TSSOP14 pin configuration
P0.1/CIN2B/KBI1/AD10 P0.0/CMP2/KBI0 P1.5/RST VSS P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL
1 2 3
14 P0.2/CIN2A/KBI2/AD11 13 P0.3/CIN1B/KBI3/AD12 12 P0.4/CIN1A/KBI4/AD13/DAC1
4 P89LPC915 11 P0.5/CMPREF/KBI5/CLKIN 5 6 7
002aaf085
10 VDD 9 8 P1.0/TXD P1.1/RXD
Fig 8.
P89LPC915 DIP14 pin configuration
P0.1/CIN2B/KBI1/AD10 P2.4/SS P1.5/RST VSS P2.3/MISO P2.2/MOSI P1.3/INT0/SDA P1.2/T0/SCL
1 2 3 4 5 6 7 8
002aaa826
16 P0.2/CIN2A/KBI2/AD11 15 P0.3/CIN1B/KBI3/AD12 14 P0.4/CIN1A/KBI4/AD13/DAC1 13 P0.5/CMPREF/KBI5/CLKIN 12 VDD 11 P2.5/SPICLK 10 P1.0/TXD 9 P1.1/RXD
P89LPC916
Fig 9.
P89LPC916 TSSOP16 pin configuration
P89LPC915_916_917_5
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Product data sheet
Rev. 05 -- 15 December 2009
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P0.1/CIN2B/KBI1/AD10 P0.0/CMP2/KBI0 P1.5/RST VSS P2.2 P1.4/INT1 P1.3/INT0/SDA P1.2/T0/SCL
1 2 3 4 5 6 7 8
002aaa827
16 P0.2/CIN2A/KBI2/AD11 15 P0.3/CIN1B/KBI3/AD12 14 P0.4/CIN1A/KBI4/AD13/DAC1 13 P0.5/CMPREF/KBI5/CLKIN 12 VDD 11 P0.7/T1/KBI7/CLKOUT 10 P1.0/TXD 9 P1.1/RXD
P89LPC917
Fig 10. P89LPC917 TSSOP16 pin configuration
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
10 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
7.2 Pin description
Table 4. Symbol P0.0 to P0.5 P89LPC915 pin description Pin Type Description I/O Port 0: Port 0 is a 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/KBI0 2 I/O O I P0.1/CIN2B/KBI1/AD10 1 I/O I I I P0.2/CIN2A/KBI2/AD11 14 I/O I I I P0.3/CIN1B/KBI3/AD12 13 I/O I I I P0.4/CIN1A/KBI4/AD13/ DAC1 12 I/O I I I I P0.5/CMPREF/KBI5/CLKIN 11 I/O I I I P1.0 to P1.5
[1]
P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output. KBI0 -- Keyboard input 0. P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD10 -- ADC1 channel 0 analog input. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD11 -- ADC1 channel 1 analog input. P0.3 -- Port 0 bit 3. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD12 -- ADC1 channel 2 analog input. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. AD13 -- ADC1 channel 3 analog input. DAC1 -- DAC1 analog output. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. CLKIN -- External clock input.
I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P89LPC915_916_917_5
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Product data sheet
Rev. 05 -- 15 December 2009
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4. Symbol P1.0/TXD P1.1/RXD
P89LPC915 pin description ...continued Pin 9 8 7 Type Description I/O O I/O I I/O I/O I/O P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C serial data input/output. P1.4 -- Port 1 bit 4. INT1 -- External interrupt 1 input. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P1.2/T0/SCL
P1.3/INT0/SDA
6
I/O I I/O
P1.4/INT1 P1.5/RST
5 3
I I I I
VSS VDD
4 10
I I
[1]
Input/output for P1.0 to P1.4. Input for P1.5.
Table 5. Symbol
P89LPC916 pin description Pin Type Description I/O Port 0: Port 0 is an 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.0 to P0.5
P89LPC915_916_917_5
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Product data sheet
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 5. Symbol
P89LPC916 pin description ...continued Pin 1 Type Description I/O I I I P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD10 -- ADC1 channel 0 analog input. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD11 -- ADC1 channel 1 analog input. P0.3 -- Port 0 bit 3. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD12 -- ADC1 channel 2 analog input. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. AD13 -- ADC1 channel 3 analog input. DAC1 -- DAC1 analog output. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. CLKIN -- External clock input.
P0.1/CIN2B/KBI1/AD10
P0.2/CIN2A/KBI2/AD11
16
I/O I I I
P0.3/CIN1B/KBI3/AD12
15
I/O I I I
P0.4/CIN1A/KBI4/AD13/DAC1 14
I/O I I I O
P0.5/CMPREF/KBI5/CLKIN
13
I/O I I I
P1.0 to P1.5
[1]
I/O, I Port 1: Port 1 is an 6-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P1.0/TXD P1.1/RXD P1.2/T0/SCL
10 9 8
I/O O I/O I I/O I/O I/O
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C serial data input/output. P1.5 -- Port 1 bit 5 (input only).
(c) NXP B.V. 2009. All rights reserved.
P1.3/INT0/SDA
7
I/O I I/O
P1.5/RST
P89LPC915_916_917_5
3
I
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8-bit microcontrollers with accelerated two-clock 80C51 core
Table 5. Symbol
P89LPC916 pin description ...continued Pin Type Description I RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:
P2.2 to P2.5
P2.2/MOSI
6
I/O I/O
P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P2.3/MISO
5
I/O I/O
P2.4/SS P2.5/SPICLK
2 11
I/O I/O I/O I/O
VSS VDD
4 12
I I
[1]
Input/output for P1.0 to P1.3. Input for P1.5.
P89LPC915_916_917_5
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Product data sheet
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 6. Symbol
P89LPC917 pin description Pin Type Description I/O Port 0: Port 0 is a 7-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.0 to P0.5, P0.7
P0.0/CMP2/KBI0
2
I/O O I
P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output. KBI0 -- Keyboard input 0. P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. AD10 -- ADC1 channel 0 analog input. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. AD11 -- ADC1 channel 1 analog input. P0.3 -- Port 0 bit 3. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. AD12 -- ADC1 channel 2 analog input. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. AD13 -- ADC1 channel 3 analog input. DAC1 -- DAC1 analog output. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. CLKIN -- External clock input.
P0.1/CIN2B/KBI1/AD10
1
I/O I I I
P0.2/CIN2A/KBI2/AD11
16
I/O I I I
P0.3/CIN1B/KBI3/AD12
15
I/O I I I
P0.4/CIN1A/KBI4/AD13/ DAC1
14
I/O I I I O
P0.5/CMPREF/KBI5
13
I/O I I I
P89LPC915_916_917_5
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Product data sheet
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8-bit microcontrollers with accelerated two-clock 80C51 core
Table 6. Symbol
P89LPC917 pin description ...continued Pin 11 Type Description I/O I/O I O P0.7 -- Port 0 bit 7. T1 -- Timer/counter 1 external count input or overflow output. KBI7 -- Keyboard input 7. CLKOUT -- Clock output.
P0.7/T1/KBI7/CLKOUT
P1.0 to P1.5
I/O, I Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type, [1] except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P1.0/TXD P1.1/RXD P1.2/T0/SCL
10 9 8
I/O O I/O I I/O I/O I/O
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. P1.2 -- Port 1 bit 2 (open-drain when used as output). T0 -- Timer/counter 0 external count input or overflow output (open-drain when used as output). SCL -- I2C serial clock input/output. P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C serial data input/output. P1.4 -- Port 1 bit 4. INT1 -- External interrupt 1 input. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
P1.3/INT0/SDA
7
I/O I I/O
P1.4/INT1 P1.5/RST
6 3
I I I I
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
16 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 6. Symbol P2.2
P89LPC917 pin description ...continued Pin 5 Type Description Port 2: Port 2 is a single bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of this Port 2 pin as an input and output depends upon the port configuration selected. Refer to Section 8.13.1 "Port configurations" and Table 15 "Static characteristics" for details. This pin has a Schmitt triggered input. I I Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
VSS VDD
4 12
[1]
Input/output for P1.0 to P1.4. Input for P1.5.
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
17 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8. Functional description
8.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
18 of 75
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Product data sheet Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved. P89LPC915_916_917_5
NXP Semiconductors
Table 7. P89LPC915 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B* BRGR0 BRGR1 BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL Accumulator ADC control register 1 ADC input select ADC mode register A ADC mode register B A/D_1 boundary high register A/D_1 boundary low register A/D_1 data register 0 A/D_1 data register 1 A/D_1 data register 2 A/D_1 data register 3 Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low 83H 82H E7H E6H 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 E0H 97H A3H C0H A1H C4H BCH D5H D6H D7H F5H A2H F0H BEH BFH BDH ACH ADH CE1 CE2 CP1 CP2 CN1 CN2 OE2 SBRGS CO1 CO2 BRGEN CMF1 CMF2 CLKLP F7 EBRR F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[2] 00[1] 00[1] 00 0000 0000 0000 0000 0000 0000 xxxx xx00 xx00 0000 xx00 0000 0000 0000 Bit address ENBI1 ADI13 BNDI1 CLK2 ENADCI 1 ADI12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 ADI10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 ADCS10 00 00 00 00 FF 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915/916/917
CPU clock divide-by-M control 95H
19 of 75
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Table 7. P89LPC915 special function registers ...continued * indicates SFRs that are bit addressable. Name FMCON Description Program flash control (Read) Program flash control (Write) FMDATA I2ADR I2CON* I2DAT I2SCLH
Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved.
Product data sheet 20 of 75
P89LPC915_916_917_5
NXP Semiconductors
SFR Bit functions and addresses addr. MSB E4H E4H E5H DBH D8H DAH DDH DCH D9H Bit address A8H Bit address E8H Bit address B8H B7H Bit address STA.4 AF EA EF EAD BF FF PAD PADH STA.3 AE EWDRT EE EST BE PWDRT PWDRT H FE PST PSTH STA.2 AD EBO ED BD PBO PBOH FD STA.1 AC ES/ESR EC BC PS/PSR PSH/ PSRH FC STA.0 AB ET1 EB BB PT1 PT1H FB 0 AA EX1 EA EC BA PX1 PX1H FA PC PCH 0 A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL I2ADR.6 DF I2ADR.5 DE I2EN I2ADR.4 DD STA I2ADR.3 DC STO I2ADR.2 DB SI I2ADR.1 DA AA I2ADR.0 D9 BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1
Reset value LSB OI FMCMD. 0 00 GC D8 CRSEL 00 00 00 0 A8 EX0 E8 EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 F8 x000 00x0 0000 0000 0000 0000 00 0000 0000 0000 0000 Hex 70 Binary 0111 0000
Program flash data I2C slave address register
Bit address I2C control register I2C data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C status register Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high
I2SCLL I2STAT IEN0* IEN1* IP0* IP0H
8-bit microcontrollers with accelerated two-clock 80C51 core
1111 1000
P89LPC915/916/917
IP1* IP1H KBCON KBMASK KBPATN
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H
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Table 7. P89LPC915 special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P0M1 P0M2 P1M1
Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved.
Product data sheet 21 of 75
P89LPC915_916_917_5
NXP Semiconductors
Reset value LSB 84 CIN1A /KB4 94 INT1 B4 83 CIN1B /KB3 93 INT0/ SDA B3 82 CIN2A /KB2 92 T0/SCL B2 81 CIN2B /KB1 91 RXD B1 80 CMP2 /KB0 90 TXD B0 0000 0000 00x0 xx00
[1] [1]
Hex
Binary
87 97 B7 SMOD1 RTCPD D7 CY RTCF
86 96 B6 SMOD0 D6 AC RTCS1
85 CMPREF /KB5 95 RST B5
Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable
84H 85H 91H 92H 87H B5H Bit address D0H F6H DFH D1H D2H D3H A9H B9H
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] BOPD VCPD D5 F0 BOF RTCS0 (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] BOI ADPD D4 RS1 POF GF1 I2PD D3 RS0 R_BK GF0 D2 OV R_WD PMOD1 SPD D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN 00 00
[3]
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11
P1M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON* SSTAT SP TAMOD
8-bit microcontrollers with accelerated two-clock 80C51 core
00 00[1]
0000 0000 0000 0000 0000 0000 xx00 000x
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
60[1][ 011x xx00
6]
P89LPC915/916/917
00[6] 00[6] 00 00 xx 9F SM0/FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 T0M2 00
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0111 xxx0 xxx0
Serial Port data buffer register 99H Bit address Serial port control Serial port extended status register Stack pointer Timer 0 and 1 auxiliary mode 98H BAH 81H 8FH
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Table 7. P89LPC915 special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
[1] [2] [3] [4] [5] [6] Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved.
Product data sheet 22 of 75
P89LPC915_916_917_5
NXP Semiconductors
Reset value LSB 8C TR0 8B IE1 8A IT1 89 IE0 88 IT0 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Hex Binary
8F TF1
8E TR1
8D TF0
Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
T1GATE RCCLK PRE2
T1C/T PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
T0GATE TRIM.3 -
T0C/T TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
FF
1111 1111
8-bit microcontrollers with accelerated two-clock 80C51 core
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
P89LPC915/916/917
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Product data sheet Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved. P89LPC915_916_917_5
NXP Semiconductors
Table 8. P89LPC916 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B* BRGR0 BRGR1 BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL Accumulator ADC control register 1 ADC input select ADC mode register A ADC mode register B A/D_1 boundary high register A/D_1 boundary low register A/D_1 data register 0 A/D_1 data register 1 A/D_1 data register 2 A/D_1 data register 3 Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low 83H 82H E7H E6H 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 E0H 97H A3H C0H A1H C4H BCH D5H D6H D7H F5H A2H F0H BEH BFH BDH ACH ADH CE1 CE2 CP1 CP2 CN1 CN2 OE2 SBRGS CO1 CO2 BRGEN CMF1 CMF2 CLKLP F7 EBRR F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[2] 00[1] 00[1] 00 0000 0000 0000 0000 0000 0000 xxxx xx00 xx00 0000 xx00 0000 0000 0000 Bit address ENBI1 ADI13 BNDI1 CLK2 ENADCI 1 ADI12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 ADI10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 ADCS10 00 00 00 00 FF 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915/916/917
CPU clock divide-by-M control 95H
23 of 75
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Table 8. P89LPC916 special function registers ...continued * indicates SFRs that are bit addressable. Name FMCON Description Program flash control (Read) Program flash control (Write) FMDATA I2ADR I2CON* I2DAT I2SCLH
Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved.
Product data sheet 24 of 75
P89LPC915_916_917_5
NXP Semiconductors
SFR Bit functions and addresses addr. MSB E4H E4H E5H DBH D8H DAH DDH DCH D9H Bit address A8H Bit address E8H Bit address B8H B7H Bit address STA.4 AF EA EF EAD BF FF PAD PADH STA.3 AE EWDRT EE EST BE PWDRT PWDRT H FE PST PSTH STA.2 AD EBO ED BD PBO PBOH FD STA.1 AC ES/ESR EC BC PS/PSR PSH/ PSRH FC STA.0 AB ET1 EB ESPI BB PT1 PT1H FB PSPI PSPIH 0 AA EA EC BA FA PC PCH 0 A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL I2ADR.6 DF I2ADR.5 DE I2EN I2ADR.4 DD STA I2ADR.3 DC STO I2ADR.2 DB SI I2ADR.1 DA AA I2ADR.0 D9 BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1
Reset value LSB OI FMCMD. 0 00 GC D8 CRSEL 00 00 00 0 A8 EX0 E8 EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 F8 x000 00x0 0000 0000 0000 0000 00 0000 0000 0000 0000 Hex 70 Binary 0111 0000
Program flash data I2C slave address register
Bit address I2C control register I2C data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C status register Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high
I2SCLL I2STAT IEN0* IEN1* IP0* IP0H
8-bit microcontrollers with accelerated two-clock 80C51 core
1111 1000
P89LPC915/916/917
IP1* IP1H KBCON KBMASK KBPATN
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H
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Table 8. P89LPC916 special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P2* P0M1 P0M2
Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved.
Product data sheet 25 of 75
P89LPC915_916_917_5
NXP Semiconductors
Reset value LSB 84 CIN1A /KB4 94 A4 SS 83 CIN1B /KB3 93 INT0/ SDA A3 MISO 82 CIN2A /KB2 92 T0/SCL A2 MOSI 81 CIN2B /KB1 91 RXD A1 80 90 TXD A0 [1] [1] [1]
Hex
Binary
87 97 A7 -
86 96 A6 -
85 CMPREF /KB5 95 RST A5 SPICLK
Port 2 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable
A0H 84H 85H 91H 92H A4H A5H 87H B5H Bit address D0H F6H DFH D1H D2H D3H A9H B9H
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] (P1M1.7) (P1M1.6) (P1M2.7) (P1M2.6) SMOD1 RTCPD D7 CY RTCF SMOD0 D6 AC RTCS1 (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) PMOD1 SPD D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN 00 00
[3]
0000 0000 11x1 xx11
P1M1 P1M2 P2M1 P2M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON*
D3[1] 00[1] FF[1] 00[1] 00 00[1]
8-bit microcontrollers with accelerated two-clock 80C51 core
00x0 xx00 11x1 xx11 00x0 xx00 0000 0000 0000 0000 0000 0000 xx00 000x
(P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) BOPD VCPD D5 F0 BOF RTCS0 BOI ADPD D4 RS1 POF GF1 I2PD D3 RS0 R_BK GF0 SPPD D2 OV R_WD -
P89LPC915/916/917
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
60[1][ 011x xx00
6]
00[6] 00[6] 00 00 xx 9F SM0/FE 9E SM1 9D SM2 9C REN 9B TB8 9A RB8 99 TI 98 RI 00
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000
Serial Port data buffer register 99H Bit address Serial port control 98H
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Table 8. P89LPC916 special function registers ...continued * indicates SFRs that are bit addressable. Name SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
[1] [2] [3] [4]
(c) NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 -- 15 December 2009 26 of 75
P89LPC915_916_917_5
NXP Semiconductors
Description Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
SFR Bit functions and addresses addr. MSB BAH 81H E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H T1GATE RCCLK PRE2 T1C/T PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 IE0 SSIG SPIF SPEN WCOL DORD MSTR CPOL CPHA SPR1 DBMOD INTLO CIDIS DBISEL FE BR OE
Reset value LSB STINT Hex 00 07 SPR0 T0M2 88 IT0 00 00 00 00 00 T0M0 TRIM.0 WDCLK 00
[5] [6] [4] [6]
Binary 0000 0000 0000 0111 0000 0100 00xx xxxx 0000 0000 xxx0 xxx0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
04 00 00 00
Bit address
8-bit microcontrollers with accelerated two-clock 80C51 core
FF
1111 1111
P89LPC915/916/917
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
[5] [6]
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Product data sheet Rev. 05 -- 15 December 2009
(c) NXP B.V. 2009. All rights reserved. P89LPC915_916_917_5
NXP Semiconductors
Table 9. P89LPC917 special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* ADCON1 ADINS ADMODA ADMODB AD1BH AD1BL AD1DAT0 AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B* BRGR0 BRGR1 BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL Accumulator ADC control register 1 ADC input select ADC mode register A ADC mode register B A/D_1 boundary high register A/D_1 boundary low register A/D_1 data register 0 A/D_1 data register 1 A/D_1 data register 2 A/D_1 data register 3 Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low 83H 82H E7H E6H 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 E0H 97H A3H C0H A1H C4H BCH D5H D6H D7H F5H A2H F0H BEH BFH BDH ACH ADH CE1 CE2 CP1 CP2 CN1 CN2 OE2 SBRGS CO1 CO2 BRGEN CMF1 CMF2 CLKLP F7 EBRR F6 ENT1 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[2] 00[1] 00[1] 00 0000 0000 0000 0000 0000 0000 xxxx xx00 xx00 0000 xx00 0000 0000 0000 Bit address ENBI1 ADI13 BNDI1 CLK2 ENADCI 1 ADI12 BURST1 CLK1 TMM1 ADI11 SCC1 CLK0 EDGE1 ADI10 SCAN1 ADCI1 ENDAC1 ENADC1 ADCS11 BSA1 E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 ADCS10 00 00 00 00 FF 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with accelerated two-clock 80C51 core
P89LPC915/916/917
CPU clock divide-by-M control 95H
27 of 75
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Table 9. P89LPC917 special function registers ...continued * indicates SFRs that are bit addressable. Name FMCON Description Program flash control (Read) Program flash control (Write) FMDATA I2ADR I2CON* I2DAT I2SCLH
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P89LPC915_916_917_5
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SFR Bit functions and addresses addr. MSB E4H E4H E5H DBH D8H DAH DDH DCH D9H Bit address A8H Bit address E8H Bit address B8H B7H Bit address STA.4 AF EA EF EAD BF FF PAD PADH STA.3 AE EWDRT EE EST BE PWDRT PWDRT H FE PST PSTH STA.2 AD EBO ED BD PBO PBOH FD STA.1 AC ES/ESR EC BC PS/PSR PSH/ PSRH FC STA.0 AB ET1 EB BB PT1 PT1H FB 0 AA EX1 EA EC BA PX1 PX1H FA PC PCH 0 A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL I2ADR.6 DF I2ADR.5 DE I2EN I2ADR.4 DD STA I2ADR.3 DC STO I2ADR.2 DB SI I2ADR.1 DA AA I2ADR.0 D9 BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1
Reset value LSB OI FMCMD. 0 00 GC D8 CRSEL 00 00 00 0 A8 EX0 E8 EI2C B8 PX0 PX0H F8 PI2C PI2CH KBIF 00[1] 00[1] 00[1] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 F8 x000 00x0 0000 0000 0000 0000 00 0000 0000 0000 0000 Hex 70 Binary 0111 0000
Program flash data I2C slave address register
Bit address I2C control register I2C data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C status register Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high
I2SCLL I2STAT IEN0* IEN1* IP0* IP0H
8-bit microcontrollers with accelerated two-clock 80C51 core
1111 1000
P89LPC915/916/917
IP1* IP1H KBCON KBMASK KBPATN
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register
F8H F7H 94H 86H
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Table 9. P89LPC917 special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address P0* Port 0 80H Bit address P1* Port 1 90H Bit address P0M1 P0M2 P1M1
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P89LPC915_916_917_5
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Reset value LSB 84 CIN1A /KB4 94 INT1 B4 83 CIN1B /KB3 93 INT0/ SDA B3 82 CIN2A /KB2 92 T0/SCL B2 81 CIN2B /KB1 91 RXD B1 80 CMP2 /KB0 90 TXD B0 0000 0000 00x0 xx00
[1] [1]
Hex
Binary
87 T1/KB7/ CLKOUT 97 B7 (P0M1.7) (P0M2.7) SMOD1 RTCPD D7 CY RTCF
86 96 B6 SMOD0 D6 AC RTCS1
85 CMPREF /KB5 95 RST B5
Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register RTC control RTC register high RTC register low Serial port address register Serial port address enable
84H 85H 91H 92H 87H B5H Bit address D0H F6H DFH D1H D2H D3H A9H B9H
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111 (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] BOPD VCPD D5 F0 BOF RTCS0 (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] BOI ADPD D4 RS1 POF GF1 I2PD D3 RS0 R_BK GF0 D2 OV R_WD PMOD1 SPD D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN 00 00
[3]
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11
P1M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON* SSTAT SP TAMOD
8-bit microcontrollers with accelerated two-clock 80C51 core
00 00[1]
0000 0000 0000 0000 0000 0000 xx00 000x
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
60[1][ 011x xx00
6]
P89LPC915/916/917
00[6] 00[6] 00 00 xx 9F SM0/FE DBMOD 9E SM1 INTLO 9D SM2 CIDIS 9C REN DBISEL 9B TB8 FE 9A RB8 BR 99 TI OE 98 RI STINT 00 00 07 T1M2 T0M2 00
0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0111 xxx0 xxx0
Serial Port data buffer register 99H Bit address Serial port control Serial port extended status register Stack pointer Timer 0 and 1 auxiliary mode 98H BAH 81H 8FH
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Table 9. P89LPC917 special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
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Reset value LSB 8C TR0 8B IE1 8A IT1 89 IE0 88 IT0 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Hex Binary
8F TF1
8E TR1
8D TF0
Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
T1GATE RCCLK PRE2
T1C/T ENCLK PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
T0GATE TRIM.3 -
T0C/T TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
FF
1111 1111
8-bit microcontrollers with accelerated two-clock 80C51 core
All ports are in input only (high-impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
P89LPC915/916/917
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.2 Enhanced CPU
The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock definitions
The P89LPC915/916/917 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 11) and can also be optionally divided to a slower frequency (see Section 8.8 "CCLK modification: DIVM register"). Note: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. PCLK -- Clock for the various peripheral devices and is CCLK2.
8.3.2 CPU clock (OSCCLK)
The P89LPC915/916/917 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock source.
8.3.3 Clock output (P89LPC917)
The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin. This allows external devices to synchronize to the P89LPC917. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.4 On-chip RC oscillator option
The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
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8-bit microcontrollers with accelerated two-clock 80C51 core
8.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the CLKIN pin. The rate may be from 0 Hz up to 18 MHz. When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
RTCS1:0 XCLK RTC RCCLK CLKIN DIVM RC OSCILLATOR (7.3728 MHz) /2 PCLK WATCHDOG OSCILLATOR (400 kHz) peripheral clock WDT RCCLK ADC1/DAC1 OSCCLK CCLK CPU CLKOUT
BAUD RATE GENERATOR
UART
TIMERS 1 AND 0
I2C
SPI (P89LPC916)
002aaa831
Fig 11. Block diagram of oscillator control
8.7 CCLK wake-up delay
The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it stabilizes. The delay is 224 OSCCLK cycles plus 60 s to 100 s.
8.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
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8-bit microcontrollers with accelerated two-clock 80C51 core
8.9 Low power select
The P89LPC915/916/917 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the power consumption further. On any reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.10 Memory organization
The various P89LPC915/916/917 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC915/916/917 devices have 2 kB of on-chip Code memory.
8.11 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in Table 10.
Table 10. Type DATA IDATA On-chip data memory usages Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Size (bytes) 128 256
8.12 Interrupts
The P89LPC915/916/917 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC915 and P89LPC917 support 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, and ADC completion. The P89LPC916 supports 14 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI, and ADC completion.
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Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
8.12.1 External interrupt inputs
The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has one external interrupt input. These external interrupt inputs are identical to those present on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt function. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.15 "Power reduction modes" for details.
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8-bit microcontrollers with accelerated two-clock 80C51 core
IE0 EX0 IE1 EX1 BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI_0 and RI_0/RI_0 ES/ESR TI_0 EST SI EI2C SPIF ESPI TI_1 and RI_1/RI_1 ES1/ESR1 TI_1 EST1 interrupt to CPU
wake-up (if in power-down)
ENADCI0 ADCI0 ENBI0 BNDI0 EADC
002aab408
Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources
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8.13 I/O ports
The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 11.
Table 11. Number of I/O pins available (P89LPC916 and P89LPC917) Reset option Number of I/O pins (16-pin package) 14 13 13 12
Clock source
RC oscillator or watchdog oscillator External clock input
No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported[1]
[1]
Required for operation above 12 MHz.
The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 12.
Table 12. Number of I/O pins available (P89LPC915) Reset option Number of I/O pins (14-pin package) 12 11 11 10
Clock source
RC oscillator or watchdog oscillator External clock input
No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported[1]
[1]
Required for operation above 12 MHz.
8.13.1 Port configurations
All but three I/O port pins on the P89LPC915/916/917 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5 (RST) can only be an input and cannot be configured. 2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open-drain. 8.13.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes.
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8-bit microcontrollers with accelerated two-clock 80C51 core
The P89LPC915/916/917 is a 3 V device, but the pins are 5 V tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.3 Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit. 8.13.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit.
8.13.2 Port 0 analog functions
The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, PT0AD bits default to `0's to enable digital functions.
8.13.3 Additional port features
After power-up, all pins are in Input-Only mode. After power-up, all I/O pins except P1.5, may be configured by software.
* Pin P1.5 is input only. * Pins P1.2 and P1.3 are configurable for either input-only or open-drain.
Every output on the P89LPC915/916/917 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 15 "Static characteristics" for detailed specifications.
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8-bit microcontrollers with accelerated two-clock 80C51 core
All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC915/916/917 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.
8.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If brownout detection is enabled the brownout condition occurs when VDD falls below the brownout trip voltage, Vbo (see Table 15 "Static characteristics"), and is negated when VDD rises above Vbo. If the P89LPC915/916/917 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 15 "Static characteristics" for specifications.
8.14.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
8.15 Power reduction modes
The P89LPC915/916/917 supports three different power reduction modes: Idle mode, Power-down mode, and total Power-down mode.
8.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
8.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC915/916/917 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake-up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.
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8-bit microcontrollers with accelerated two-clock 80C51 core
Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
8.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.
8.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1); Power-on detect; Brownout detect; Watchdog timer; Software reset; UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a `0' to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set. 8.17 Timers/counters 0 and 1
The P89LPC915/916/917 have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 and/or T1 pins upon timer overflow has been added.
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In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle. Timer 0 has five operating modes (Modes 0, 1, 2, 3 and 6). Timer 1 has four operating modes (Modes 0, 1, 2, and 3), except on the P89LPC917 where Timer 1 also has Mode 6. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.
8.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
8.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
8.17.6 Timer overflow toggle output
Timer 0 (and Timer 1 on the P89LPC917) can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
8.18 RTC/system timer
The P89LPC915/916/917 have a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down-counter comprised of a 7-bit prescaler and a 16-bit loadable down-counter. When it reaches all `0's, the counter will be reloaded again and the RTCF flag will be set.
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The clock source for this counter can be either the CPU clock (CCLK) or the external clock input, provided that the external clock input is not being used as the CPU clock. If the external clock input is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state.
8.19 UART
The P89LPC915/916/917 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC915/916/917 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
8.19.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
8.19.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8_n in Special Function Register SnCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.19.5 "Baud rate generator and selection").
8.19.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of `0' or `1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer 1 output rate available to the UART.
8.19.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.19.5 "Baud rate generator and selection").
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8.19.5 Baud rate generator and selection
Each enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or its baud rate generator output (see Figure 13). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses OSCCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa897
Fig 13. Baud rate sources for UART (Modes 1, 3)
8.19.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is `1', framing errors can be made available in SCON.7 respectively. If SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON [7:6]) are set up when SMOD0 is `0'.
8.19.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.
8.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.
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8.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
8.20 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 14. The P89LPC915/916/917 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
RPU
RPU
SDA I2C-bus SCL P1.3/SDA P1.2/SCL I2C MCU OTHER DEVICE WITH I2C-BUS INTERFACE OTHER DEVICE WITH I2C-BUS INTERFACE
002aab410
Fig 14. I2C-bus configuration
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8
ADDRESS REGISTER P1.3
I2ADR
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT 8
CCLK TIMING AND CONTROL LOGIC interrupt
INPUT FILTER P1.2/SCL OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL
SERIAL CLOCK GENERATOR
CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8
status bus
STATUS DECODER
I2STAT
STATUS REGISTER
8
002aaa899
Fig 15. I2C-bus serial interface block diagram
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INTERNAL BUS
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8.21 SPI
The P89LPC916 provides another high-speed serial communication interface--the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master mode or up to 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
S M CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S PIN CONTROL LOGIC
MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPEN
002aaa900
(c) NXP B.V. 2009. All rights reserved.
SPI clock (master) SELECT SPR1 SPR0
clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus
SPI CONTROL WCOL SPIF
MSTR SPEN SPR0 SSIG SPI interrupt request
SPI STATUS REGISTER
Fig 16. SPI block diagram
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
* SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
* SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 17 through Figure 19.
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8.21.1 Typical SPI configurations
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR PORT
SPICLK SS
002aaa901
Fig 17. SPI single master single slave configuration
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR SS
SPICLK SS SPI CLOCK GENERATOR
002aaa902
Fig 18. SPI dual device configuration, where either can be a master or a slave
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master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR port
SPICLK SS
slave MISO MOSI 8-BIT SHIFT REGISTER
SPICLK port SS
002aaa903
Fig 19. SPI single master multiple slaves configuration
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8.22 Analog comparators
Two analog comparators are provided on the P89LPC915/916/917. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 20. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(bg) CN1 change detect CMF1 comparator 1 CO1 OE1
CMP1 (P0.6)
interrupt change detect CP2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2
002aaa904
EC
comparator 2
Fig 20. Comparator input and output connections
8.22.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V 10 %.
8.22.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
8.22.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.
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If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
8.23 KBI
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.
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8.24 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 21 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC915/916/917 User's Manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog oscillator PCLK
/32
PRESCALER
8-BIT DOWN COUNTER
reset(1)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 21. Watchdog timer in Watchdog mode (WDTE = 1)
8.25 Additional features
8.25.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
8.25.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
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8.26 Flash program memory
8.26.1 General description
The P89LPC915/916/917 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC915/916/917 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC915/916/917 uses VDD as the supply voltage to perform the Program/Erase algorithms.
8.26.2 Features
* * * * * * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ICP. Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 100,000 typical erase/program cycles for each byte. 10 year minimum data retention.
8.26.3 Flash organization
The program memory consists of eight 256-byte sectors on the P89LPC915/916/917 devices. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
8.26.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
8.26.5 Flash programming and erasing
Two different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space.
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8.26.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC915/916/917 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application--using commercially available programmers--possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC915/916/917 User's Manual.
8.26.7 IAP-Lite
IAP-Lite is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The IAP-Lite operations are accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC915/916/917 User's Manual.
8.26.8 Power-on reset code execution
The P89LPC915/916/917 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC915/916/917 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H. Table 13 shows the factory default Boot Vector setting for this device. While these devices do not contain a factory bootloader, the Boot Vector and Status bit do provide a mechanism for an alternate code execution at reset.
Table 13. Device P89LPC915 P89LPC916 P89LPC917 Default boot vector and Status bit values Default boot vector 00H 00H 00H Default Status bit 0 0 0
8.26.9 Hardware activation of the alternate code
The alternate code execution address can be forced during a power-on sequence (see the P89LPC915/916/917 User's Manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code starting at address 0000H but can be manually forced into executing from an alternated address using the Boot Vector. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
8.27 User configuration bytes
Some user-configurable features of the P89LPC915/916/917 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC915/916/917 User's Manual for additional details.
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8.28 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC915/916/917. Each byte corresponds to one sector. Please see the P89LPC915/916/917 User's Manual for additional details.
9. A/D converter
9.1 General description
The P89LPC915/916/917 devices have a single 8-bit, 4-channel multiplexed analog-to-digital converter with a DAC module. A block diagram of the A/D converter is shown in Figure 22. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.
9.2 Features
I Single 8-bit, 4-channel multiplexed input, successive approximation A/D converter. I Four A/D result registers. I Six operating modes: N Fixed channel, single conversion mode. N Fixed channel, continuous conversion mode. N Auto scan, single conversion mode. N Auto scan, continuous conversion mode. N Dual channel, continuous conversion mode. N Single step mode. I Three conversion start modes: N Timer triggered start. N Start immediately. N Edge triggered. I 8-bit conversion time of 3.9 s at an A/D clock of 3.3 MHz. I Interrupt or polled operation. I Boundary limits interrupt. I DAC output to a port pin with high output impedance. I Clock divider. I Power-down mode.
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9.3 Block diagram
comp + INPUT MUX SAR -
DAC1
8
CONTROL LOGIC comp + INPUT MUX SAR -
DAC0
8
CCLK
002aab080
Fig 22. ADC block diagram
9.4 A/D operating modes
9.4.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes.
9.4.2 Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user.
9.4.3 Auto scan, single conversion mode
Any combination of the four input channels can be selected for conversion. A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.
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9.4.4 Auto scan, continuous conversion mode
Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the four result registers, overwriting the previous results.Continous conversions continue until terminated by the user.
9.4.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. The result of the conversion of the first channel is placed in result register, AD1DAT0. The result of the conversion of the second channel is placed in result register, AD1DAT1. The first channel is again converted and its result stored in AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).
9.4.6 Single step mode
This special mode allows `single-stepping' in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. May be used with any of the start modes.
9.5 Conversion start modes
9.5.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes.
9.5.2 Start immediately
Programming this mode immediately starts a conversion.This start mode is available in all A/D operating modes.
9.5.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes.
9.6 Boundary limits interrupt
The A/D converter has both a high and low boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable.
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9.7 DAC output to a port pin with high output impedance
The A/D converter's DAC block can be output to a port pin. In this mode, the AD1DAT3 register is used to hold the value fed to the DAC. After a value has been written to the DAC (written to AD1DAT3), the DAC output will appear on the channel 3 pin.
9.8 Clock divider
The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose.
9.9 Power-down and Idle mode
In Idle mode the A/C converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D.
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10. Limiting values
Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/O(tot)(max) Vn Ptot(pack) Parameter operating bias ambient temperature storage temperature range HIGH-level output current per I/O pin LOW-level output current per I/O pin maximum total I/O current voltage on any pin (except VSS) total power dissipation per package with respect to VDD based on package heat transfer, not device power consumption Conditions Min -55 -65 Max +125 +150 8 20 120 3.5 1.5 Unit C C mA mA mA V W
[1]
The following applies to Table 14: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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11. Static characteristics
Table 15. Static characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified. Symbol IDD(oper) IDD(idle) IDD(pd) Parameter operating supply current Idle mode supply current power supply current, power-down mode, voltage comparators powered-down total Power-down mode supply current rise rate fall rate power-on reset voltage data retention voltage HIGH-LOW threshold voltage LOW-level input voltage LOW-HIGH threshold voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except SCL, SDA SCL, SDA only except SCL, SDA SCL, SDA only port 1 IOL = 20 mA; all ports except SCL, SDA IOL = 10 mA; all ports except SCL, SDA IOL = 3.2 mA; all ports except SCL, SDA VOH HIGH-level output voltage IOH = -8 mA; push-pull mode; all ports except SCL, SDA IOH = -3.2 mA; push-pull mode; all ports except SCL, SDA IOH = -20 A; quasi-bidirectional mode; all ports except SCL, SDA Vxtal Vn Ciss IIL crystal voltage voltage on any pin (except XTAL1, XTAL2, VDD) input capacitance logical 0 input current VI = 0.4 V voltage on XTAL1, XTAL2 pins with respect to VSS with respect to VSS
[5] [4]
Conditions VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz VDD = 3.6 V, industrial VDD = 3.6 V, extended VDD = 3.6 V, industrial VDD = 3.6 V, extended of VDD of VDD
[2] [2] [2] [2] [2] [2] [3] [3]
Min -
Typ[1] 7 11 3.6 4 45 -
Max 13 16 4.8 6 70 150 5 50 2 50 0.2 0.3VDD 0.7VDD 5.5 1.0 0.3 0.3 -
Unit mA mA mA mA A A A A mV/s mV/s V V V V V V V V V V V
IDD(tpd) (dV/dt)r (dV/dt)f VPOR VDDR Vth(HL) VIL Vth(LH) VIH Vhys VOL
1.5 0.22VDD -0.5 0.7VDD VDD - 1
<0.1 0.4VDD 0.6VDD 0.2VDD 0.6 0.2 0.2 -
VDD - 0.7
VDD - 0.4
-
V
VDD - 0.3
VDD - 0.2
-
V
-0.5 -0.5 -
-
+4.0 +5.5 15 -80
V V pF A
[6] [7]
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Table 15. Static characteristics ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified. Symbol ILI ITL RRST(int) Vbo Vref(bg) TCbg Parameter input leakage current logical 1-to-0 transition current, all ports internal pull-up resistance on pin RST brownout trip voltage band gap reference voltage band gap temperature coefficient 2.4 V < VDD < 3.6 V; with BOV = 1, BOPD = 0 Conditions VI = VIL, VIH or Vth(HL) VI = 1.5 V at VDD = 3.6 V
[8] [9]
Min -30 10 2.40 1.11 -
Typ[1] 1.23 10
Max 10 -450 30 2.70 1.34 20
Unit A A k V V ppm/C
[1] [2] [3] [4] [5]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer. The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. See Section 10 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
[6] [7] [8] [9]
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12. Dynamic characteristics
Table 16. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol fosc(RC) fosc(WD) fCLKLP Glitch filter tgr glitch rejection time P1.5/RST pin any pin except P1.5/RST tsa signal acceptance time P1.5/RST pin any pin except P1.5/RST External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time see Figure 28 see Figure 28 see Figure 28 see Figure 28 see Figure 28 see Figure 27 0 83 33 33 16Tcy(CLK) 13Tcy(CLK) 150 12 Tcy(CLK) - tCLCX Tcy(CLK) - tCHCX 8 8 Tcy(CLK) + 20 0 33 33 1333 1083 150 8 8 103 0 MHz ns ns ns ns ns ns ns ns ns ns 125 50 50 15 125 50 50 15 ns ns ns ns Parameter internal RC oscillator frequency internal watchdog oscillator frequency low power select clock frequency Conditions industrial extended Variable clock Min 7.189 7.004 320 0 Max 7.557 7.741 520 8 fosc = 12 MHz Min 7.189 7.004 320 Max 7.557 MHz 7.741 MHz 520 kHz MHz Unit
Shift register (UART mode 0) output data set-up to clock rising see Figure 27 edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master TSPICYC SPI cycle time slave master see Figure 23, 24, 25, 26 0 6 CCLK 4 CCLK CCLK CCLK 6 4
see Figure 27 see Figure 27 see Figure 27
SPI interface fSPI 0 500 333 2.0 3.0 MHz MHz ns ns
-
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Table 16. Dynamic characteristics (12 MHz) ...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol tSPILEAD tSPILAG tSPICLKH Parameter SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 25, 26
Variable clock Min 250 Max 120 240
fosc = 12 MHz Min 250 250 165 250 165 250 100 100 0 Max 120 240
Unit
ns ns ns ns ns ns ns ns ns ns
see Figure 25, 26 250 see Figure 23, 24, 25, 26
2 CCLK 3 CCLK
see Figure 23, 24, 25, 26
2 CCLK 3 CCLK
see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 25, 26
100 100 0
see Figure 25, 26 0 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 0 240 167 0 240 167 ns ns ns
-
100 2000
-
100 2000
ns ns
see Figure 23, 24, 25, 26
-
100 2000
-
100 2000
ns ns
Parameters are valid over ambient temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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Table 17. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol fosc(RC) fosc(WD) fCLKLP Glitch filter tgr glitch rejection time P1.5/RST pin any pin except P1.5/RST tsa signal acceptance time P1.5/RST pin any pin except P1.5/RST External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time see Figure 28 see Figure 28 see Figure 28 see Figure 28 see Figure 28 see Figure 27 see Figure 27 see Figure 27 0 55 22 22 16Tcy(CLK) 13Tcy(CLK) 150 18 Tcy(CLK) - tCLCX Tcy(CLK) - tCHCX 5 5 Tcy(CLK) + 20 0 22 22 888 722 150 5 5 75 0 MHz ns ns ns ns ns ns ns ns ns ns 125 50 50 15 125 50 50 15 ns ns ns ns Parameter Conditions Variable clock Min internal RC oscillator frequency industrial extended internal watchdog oscillator frequency low power select clock frequency 7.189 7.004 320 0 Max 7.557 7.741 520 8 fosc = 18 MHz Unit Min 7.189 7.004 320 Max 7.557 MHz 7.741 MHz 520 kHz MHz
Shift register (UART mode 0)
input data hold after clock rising see Figure 27 edge time input data valid to clock rising edge time SPI operating frequency slave master see Figure 27
SPI interface fSPI 0 see Figure 23, 24, 25, 26
6 4 CCLK 6 CCLK 4
0 333 222 250 250
3.0 4.5 -
MHz MHz ns ns ns ns
TSPICYC
SPI cycle time slave master
CCLK CCLK
-
tSPILEAD tSPILAG
SPI enable lead time slave SPI enable lag time
see Figure 25, 26 250 see Figure 25, 26 250
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Table 17. Dynamic characteristics (18 MHz) ...continued VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol tSPICLKH Parameter SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2] Parameters are valid over ambient temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
Conditions see Figure 23, 24, 25, 26
Variable clock Min
2 3
fosc = 18 MHz Unit Min 111 167 111 167 100 100 0 Max 80 160 ns ns ns ns ns ns ns ns
Max 80 160
CCLK CCLK
see Figure 23, 24, 25, 26
2 3
CCLK CCLK
see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 25, 26
100 100 0
see Figure 25, 26 0 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 0 160 111 0 160 111 ns ns ns
-
100 2000
-
100 2000
ns ns
see Figure 23, 24, 25, 26
-
100 2000
-
100 2000
ns ns
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12.1 Waveforms
SS TSPICYC tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR master MSB/LSB out master LSB/MSB out
002aaa908
tSPICLKL
tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF
Fig 23. SPI master timing (CPHA = 0)
SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH
SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPICLKH tSPICLKL tSPIR
tSPIDSU MISO (input)
tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa909
Fig 24. SPI master timing (CPHA = 1)
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SS
tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV MISO (output) tSPIF
TSPICYC tSPICLKH tSPICLKL tSPIR tSPILAG
tSPIR
tSPICLKL
tSPIR tSPICLKH
tSPIOH tSPIDV
tSPIOH
tSPIDIS
slave MSB/LSB out
slave LSB/MSB out
not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa910
Fig 25. SPI slave timing (CPHA = 0)
SS tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) not defined slave MSB/LSB out slave LSB/MSB out tSPICLKL tSPIR tSPICLKH tSPIF tSPICLKH tSPIR tSPIR tSPILAG
TSPICYC tSPICLKL
tSPIOH tSPIDV
tSPIOH tSPIDV tSPIDIS
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa911
Fig 26. SPI slave timing (CPHA = 1)
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TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 27. Shift register mode timing
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 28. External clock timing
12.2 ISP entry mode
Table 18. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified. Symbol tVR tRH tRL Parameter VDD active to RST active delay time RST HIGH time RST LOW time Conditions Min 50 1 1 Typ Max 32 Unit s s s
VDD tVR RST tRL
002aaa912
tRH
Fig 29. ISP entry timing
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13. Other characteristics
13.1 Comparator electrical characteristics
Table 19. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common mode input voltage common mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 20 VDD - 0.3 -50 500 10 10
Unit mV V dB ns s A
-
0 < VI < VDD
-
This parameter is characterized, but not tested in production.
13.2 ADC electrical characteristics
Table 20. ADC electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C, or -40 C to +125 C (see Table 3 on page 3), unless otherwise specified. All limits valid for an external source impedance of less than 10 k. Symbol VIA Cia ED EL(adj) EO EG Eu(tot) MCTC ct(port) SRin Tcy(ADC) tADC Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error total unadjusted error channel-to-channel matching crosstalk between port inputs input slew rate ADC clock cycle conversion time A/D enabled 0 kHz to 100 kHz Conditions Min 111 Typ Max VSS + 0.2 15 1 1 2 1 2 1 -60 100 2000 13Tcy(ADC) Unit V pF LSB LSB LSB % LSB LSB dB V/ms ns ns VSS - 0.2 -
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14. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 14 8 MH wM (e 1)
pin 1 index E
1
7
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 30. Package outline SOT27-1 (DIP14)
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P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 31. Package outline SOT402-1 (TSSOP14)
P89LPC915_916_917_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
69 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 32. Package outline SOT403-1 (TSSOP16)
P89LPC915_916_917_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
70 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
15. Abbreviations
Table 21. Acronym ADC CPU CCU DAC EPROM EEPROM EMI PLL PWM RAM RC RTC SAR SFR SPI UART Acronym list Description Analog to Digital Converter Central Processing Unit Capture/Compare Unit Digital to Analog Converter Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory ElectroMagnetic Interference Phase-Locked Loop Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
71 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
16. Revision history
Table 22. Revision history Release date 20091215 Data sheet status Product data sheet Change notice Supersedes P89LPC915_916_917-04 Document ID P89LPC915_916_917_5 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added ADC electrical characteristics, Table 20. Added P89LPC915FN. Product data Preliminary data Preliminary data Preliminary data P89LPC915_916_917-03 P89LPC915_916_917-02 P89LPC915_916_917-01 -
P89LPC915_916_917-04 20041217 P89LPC915_916_917-03 20040701 P89LPC915_916_917-02 20040512 P89LPC915_916_917-01 20040408
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
72 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
73 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 Product comparison overview . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Functional description . . . . . . . . . . . . . . . . . . 18 8.1 Special function registers . . . . . . . . . . . . . . . . 18 8.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 31 8.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 31 8.3.3 Clock output (P89LPC917) . . . . . . . . . . . . . . . 31 8.4 On-chip RC oscillator option . . . . . . . . . . . . . . 31 8.5 Watchdog oscillator option . . . . . . . . . . . . . . . 31 8.6 External clock input option . . . . . . . . . . . . . . . 32 8.7 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 32 8.8 CCLK modification: DIVM register . . . . . . . . . 32 8.9 Low power select . . . . . . . . . . . . . . . . . . . . . . 33 8.10 Memory organization . . . . . . . . . . . . . . . . . . . 33 8.11 Data RAM arrangement . . . . . . . . . . . . . . . . . 33 8.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.12.1 External interrupt inputs . . . . . . . . . . . . . . . . . 34 8.13 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.13.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 36 8.13.1.1 Quasi-bidirectional output configuration . . . . . 36 8.13.1.2 Open-drain output configuration . . . . . . . . . . . 37 8.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 37 8.13.1.4 Push-pull output configuration . . . . . . . . . . . . 37 8.13.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 37 8.13.3 Additional port features. . . . . . . . . . . . . . . . . . 37 8.14 Power monitoring functions. . . . . . . . . . . . . . . 38 8.14.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 38 8.14.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . 38 8.15 Power reduction modes . . . . . . . . . . . . . . . . . 38 8.15.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.15.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 38 8.15.3 Total Power-down mode . . . . . . . . . . . . . . . . . 39 8.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.17 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 39 8.17.1 8.17.2 8.17.3 8.17.4 8.17.5 8.17.6 8.18 8.19 8.19.1 8.19.2 8.19.3 8.19.4 8.19.5 8.19.6 8.19.7 8.19.8 8.19.9 8.19.10 8.20 8.21 8.21.1 8.22 8.22.1 8.22.2 8.22.3 8.23 8.24 8.25 8.25.1 8.25.2 8.26 8.26.1 8.26.2 8.26.3 8.26.4 8.26.5 8.26.6 8.26.7 8.26.8 8.26.9 8.27 8.28 9 9.1 9.2 9.3 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Using flash as data storage . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on reset code execution . . . . . . . . . . . Hardware activation of the alternate code . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 40 40 40 41 41 41 41 41 42 42 42 42 42 43 43 45 46 48 48 48 48 49 50 50 50 50 51 51 51 51 51 51 52 52 52 52 52 53 53 53 53 54
continued >>
P89LPC915_916_917_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 15 December 2009
74 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
54 54 54 54 55 55 55 55 55 55 55 55 56 56 56 57 58 60 64 66 67 67 67 68 71 72 73 73 73 73 73 73 74
9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 9.5.1 9.5.2 9.5.3 9.6 9.7 9.8 9.9 10 11 12 12.1 12.2 13 13.1 13.2 14 15 16 17 17.1 17.2 17.3 17.4 18 19
A/D operating modes . . . . . . . . . . . . . . . . . . . Fixed channel, single conversion mode . . . . . Fixed channel, continuous conversion mode . Auto scan, single conversion mode . . . . . . . . Auto scan, continuous conversion mode . . . . Dual channel, continuous conversion mode . . Single step mode . . . . . . . . . . . . . . . . . . . . . . Conversion start modes . . . . . . . . . . . . . . . . . Timer triggered start . . . . . . . . . . . . . . . . . . . . Start immediately . . . . . . . . . . . . . . . . . . . . . . Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . Boundary limits interrupt. . . . . . . . . . . . . . . . . DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down and Idle mode . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . ADC electrical characteristics . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 December 2009 Document identifier: P89LPC915_916_917_5

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